1. Technical Field
The present invention relates to an image capturing apparatus.
2. Related Art
An image capturing substrate configured by arranging, in a matrix, pixels each including an image capturing apparatus is mounted on a mobile phone, for example. The image capturing substrate includes, as types, an image capturing substrate including an image capturing apparatus of CCD (Carrier-Coupled Device) type, and an image capturing substrate including an image capturing apparatus of a MOS type. The CCD-type image capturing substrate is of excellent image quality, and the MOS-type image capturing substrate is less in power consumption and low in process cost. In recent years, proposed is a MOS-type image capturing substrate operating in the mode of threshold voltage modulation, offering both high image quality and low power consumption. The MOS-type image capturing substrate operating in the mode of threshold voltage modulation is described in Japanese Patent No. 3313683.
The image capturing substrate derives an image output by pixels being arranged in a matrix, and by the pixels each being repeatedly in the state of clearance, storage, and reading. In the image capturing substrate described in Japanese Patent No. 3313683, the pixels each include a photodiode for use of storage and a transistor for use of reading (hereinafter, referred to as modulation because it is an operation of indicating an operation of extracting any threshold modulation component by a light-generating carrier).
FIG. 8 is a diagram showing the schematic wiring of an image capturing substrate 100 described in Japanese Patent No. 3313683 in which pixels 3 each including a VMIS-type image capturing apparatus 120 being a combination of a photodiode PD and a modulation transistor TM are arranged in a matrix (it is used also as an equivalent circuit diagram indicating the state in which an intense light SL enters into the configuration not including a transfer transistor TS that will be described later). An output from a source section 7 of each of the pixels 3 arranged in the same row is extracted via a source line 66 of shared use. Among the pixels 3 connected to the same source line 66, supplying an ON signal to any one gate line 67 enables reading of only a signal from the source section 7 of any one of the pixels 3 connected to the gate line 67 provided with the ON signal. In this case, the selection of such a pixel 3 is made by applying a potential higher than that of a not-selected ring gate electrode 6a of a not-selected modulation transistor TMa of a not-selected pixel 3a to a ring gate electrode 6 of the modulation transistor TM of the (selected) pixel 3 for reading.
As an ON signal, the output from the source section 7 of the modulation transistor TM applied with a high gate potential will be higher than an output from a not-selected source section 7a of the not-selected modulation transistor TMa applied with a low gate potential. The output from the source section 7 of the selected pixel 3 corresponding to the gate line 67 selected by the ON signal can be derived from a source line 66x. 
Herein, as the procedure for signal extraction in FIG. 8, attention is given to the source line 66x. Extracted is a difference, in terms of potential, between the source line 66x that is under the control of the potential coming from the source section 7 of the pixel 3 selected after the storage of light-generating carriers and the source line 66x that is under the control of the potential being an output of the source section 7 of the pixel 3 after the clearance. By extracting such a difference between the potential of the source line 66x after the storage and the potential of the source line 66x after the clearance, any variations among the pixels 3 caused by the characteristics distribution such as threshold value can be cancelled out, thereby being able to extract an image signal with a higher SN ratio.
For such a difference extraction, with the configuration described in Japanese Patent No. 3313683, the gate line 67 selected as shown in FIG. 8 is used for a selection of the pixel 3, and the potential from the source section 7 of the selected pixel 3 is transferred to each of the source lines 66 so that the potential from the source section 7 of the selected pixel 3 is detected. Herein, when an intense light SL enters into a not-selected photodiode PDa of the not-selected pixel 3a leading to the source line 66x, there may be a case of generating a potential higher than the potential from the source section 7 of the selected pixel 3. The reason thereof is considered that the not-selected source section 7a of the not-selected modulation transistor TMa is increased in potential, and by shifting the source potential by application of the potential to the ring gate electrode 6, the resulting potential exceeds the source potential of the selected modulation transistor TM.
In this case, compared with the potential of the source section 7 after the clearance, the potential of the not-selected source section 7a belonging to the not-selected pixel 3a receiving the intense light SL becomes higher. That is, the potential of the source line 66x of the selected pixel 3 is reduced down only to the potential of the not-selected source section 7a of the not-selected pixel 3, being higher than the potential of the source section 7 of the pixel 3 selected after the clearance. Therefore, in this case, no difference can be derived between the potential of the source section 7 of the selected pixel 3 after the storage of the light-generating carriers being outputs from the source section 7 and the potential of the source section 7 after the clearance.
With no difference as such, provided is a difference, in terms of potential, between the source section 7 after the storage of the light-generating carriers and the not-selected source section 7a of the not-selected pixel 3a exposed with the intense light SL, and thus the light intensity seems to be reduced for output, thereby causing a phenomenon called black smear.
To prevent such black smear, as shown in Japanese Patent No. 3720014, there is a technology of forming a pixel using three transistors. However, it means the number of transistors for a pixel is increased to three, and there is thus a problem of reducing the aperture ratio and reducing the light sensitivity.